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ADT7490
Table 87. REGISTER 0x73 ? CONFIGURATION REGISTER 2 (POWER-ON DEFAULT = 0x00)
Bit No.
0
1
2
3
4
5
6
Mnemonic
FanPresDT
Fan1Detect
Fan2Detect
Fan3Detect
AVG
ATTN
CONV
R/W (Note 1)
R/W
Read-only
Read-only
Read-only
R/W
R/W
R/W
Description
When FanPresDT = 1, the state of Bits [3:1] of this register reflects the presence of a 4-wire
fan on the appropriate TACH channel.
Fan1Detect = 1 indicates that a 4-wire fan is connected to the PWM1 input.
Fan2Detect = 1 indicates that a 4-wire fan is connected to the PWM2 input.
Fan3Detect = 1 indicates that a 4-wire fan is connected to the PWM3 input.
AVG = 1 indicates that averaging on the temperature and voltage measurements is turned
off. This allows measurements on each channel to be made much faster (x16).
ATTN = 1 indicates that the ADT7490 removes the attenuators from the +2.5 V IN , V CCP ,
+5 V IN , and +12 V IN inputs. These inputs can be used for other functions such as connecting
up external sensors. It is also possible to remove attenuators from individual channels using
Bits [7:4] of Configuration Register 4 (0x7D).
CONV = 1 indicates that the ADT7490 is put into a single-channel ADC conversion mode. In
this mode, the ADT7490 can be made to read continuously from one input only, for example,
Remote 1 temperature. The appropriate ADC channel is selected by writing to Bits [7:4] of
TACH1 minimum high byte register (0x55).
When CONV = 1, Bits [7:4], Register 0x55
Bit Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
ADC Channel Selected
+2.5 V IN
V CCP
V CC
+5 V IN
+12 V IN
Remote 1 Temperature
Local Temperature
Remote 2 Temperature
V TT
I MON
7
Shutdown
R/W
When the shutdown bit is set to 1, the ADT7490 goes into shutdown mode.
1. This register becomes read-only when the Configuration Register 1 (0x40) Lock bit is set to 1. Any further attempts to write to this register
have no effect.
Table 88. REGISTER 0x74 ? INTERRUPT MASK REGISTER 1 (POWER-ON DEFAULT = 0x00)
Bit No.
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Mnemonic
+ 2.5  V IN /
THERM
V CCP
V CC
+5 V IN
R1T
LT
R2T
OOL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
+2.5 V IN /THERM = 1 masks SMBALERT for out-of-limit conditions on the +2.5 V IN /THERM
timer channel.
V CCP = 1 masks SMBALERT for out-of-limit conditions on the V CCP channel.
V CC = 1 masks SMBALERT for out-of-limit conditions on the V CC channel.
+5 V IN = 1 masks SMBALERT for out-of-limit conditions on the +5 V IN channel.
R1T = 1 masks SMBALERT for out-of-limit conditions on the Remote 1 temperature channel.
LT = 1 masks SMBALERT for out-of-limit conditions on the local temperature channel.
R2T = 1 masks SMBALERT for out-of-limit conditions on the Remote 2 temperature channel.
OOL = 1 masks SMBALERT assertions when the OOL status bit is set.
Note that the OOL mask bit is independent of the individual mask bits associated with
Interrupt Status Register 2. Therefore, if the intention is to mask SMBALERT assertions for
any of the Interrupt Status Register 2 bits, OOL must also be masked.
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